Static random access memories (SRAMs) are generally used in applications requiring high speed, such as memory in a data processing system. Each SRAM cell stores one bit of data and is implemented as a pair of cross-coupled inverters. The SRAM cell is only stable in one of two possible voltage levels. The logic state of the cell is determined by whichever of the two inverter outputs is a logic high, and can be made to change states by applying a voltage of sufficient magnitude and duration to the appropriate cell input. The stability of a SRAM cell is an important issue. The SRAM cell must be stable against transients, process variations, soft errors, and power supply fluctuations which may cause the cell to inadvertently change logic states. Also, the SRAM cell should ideally provide good stability during read operations without harming speed or the ability to write to the cell.
A two-port SRAM cell has a write word line and a read word line. A read port of the SRAM cell may include a pair of series-connected MOS (metal-oxide semiconductor) transistors coupled between a power supply terminal and a read bit line. A gate of one transistor is coupled to a storage node of the cell and the gate of the other transistor is connected to the read word line. Using a separate read port in this manner provides the advantage of having little or no adverse effect on cell stability or the write margin.
Low voltage operation is becoming more common for SRAM in portable applications. Today, power supply voltages for an active memory cycle may be in the range of one volt or less. Providing a low voltage SRAM with adequate write margins and with good cell stability may be difficult and usually comes at the expense of lower read and write performance.
Therefore, there is a need for a SRAM having improved write margins at low power supply voltages without decreasing cell stability.